代码搜索：Vector
找到约 10,000 项符合「Vector」的源代码
代码结果 10,000
www.eeworm.com/read/360651/10082950
m lsp_get_tdist.m
function o=lsp_get_tdist(W,candidate_LSP_vector,target_LSP_vector,P)
%W--weight coef
%P--present MA prediction coef
%o--distortion for present MA
for i=1:10
temp(i)=(candidate_LSP_vector(i)-t
www.eeworm.com/read/359579/10135489
m main_gp_algorithm.m
% G-P 算法求关联维(输入时间序列数据)
% 使用平台 - Matlab6.5 / Matlab7.0
% 作者：陆振波，海军工程大学
% 欢迎同行来信交流与合作，更多文章与程序下载请访问我的个人主页
% 电子邮件：luzhenbo@yahoo.com.cn
% 个人主页：http://luzhenbo.88uu.com.cn
clc
clear
close all
%----------
www.eeworm.com/read/162699/10281962
vhd altera_vhdl_support.vhd
-- ----------------------------------------------------------------------------
--
-- These routines are used to help SOPC Builder generate VHDL code.
--
-- -----------------------------------
www.eeworm.com/read/353880/10408677
vhd output.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantia
www.eeworm.com/read/353400/10449902
vhd rom.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity rom is
port(
clk : in std_logic;
DOUT : out std_logic_vector(7 downto 0)
);
end ;
architecture a of r
www.eeworm.com/read/424281/10467144
c diff.c
/* multimin/diff.c
*
* Copyright (C) 2000 David Morrison
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as publi
www.eeworm.com/read/424281/10474391
c view_source.c
/* vector/view_source.c
*
* Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2007 Gerard Jungman, Brian Gough
*
* This program is free software; you can redistribute it and/or modify
* it unde
www.eeworm.com/read/424281/10474570
c test_complex_source.c
/* vector/test_complex_source.c
*
* Copyright (C) 1996, 1997, 1998, 1999, 2000, 2007 Gerard Jungman, Brian Gough
*
* This program is free software; you can redistribute it and/or modify
* it un
www.eeworm.com/read/423926/10525931
vhd toplevel_dualport_ram_xilinxcore.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopLevel_DualPort_Ram_XilinxCore is
port(
WriteAddress,ena,enb,WenableA,WenableB: in st
www.eeworm.com/read/160403/10535316
vhd fortest.vhd
-- VHDL Test Bench Created from source file lms.vhd -- 22:08:05 07/05/2005
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the