rom.vhd

来自「我用VHDL写的正弦」· VHDL 代码 · 共 34 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity rom is
port(
     clk : in std_logic;
	 DOUT :	out std_logic_vector(7 downto 0)
);
end ;
architecture a of rom is
component  romexam IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;

signal q1:std_logic_vector(5 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1' and clk'last_value='0') then
    if(q1<"111111")then
	q1<=q1+1;
	else
	q1<="000000";
	end if;
end if;
end process;
u1:romexam port map(address=>q1,q=>dout,clock=>clk);
end a;