toplevel_dualport_ram_xilinxcore.vhd

Top Level Dual Port Ram Core Project, VHDL code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopLevel_DualPort_Ram_XilinxCore is
port(
WriteAddress,ena,enb,WenableA,WenableB: in std_logic;
ReadAddress: in std_logic;
SystemClock: in std_logic;
DataIn: in std_logic_vector (3 downto 0);
DataOutA: out std_logic_vector (3 downto 0);
DataOutB: out std_logic_vector (3 downto 0);
An: out std_logic_vector (3 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp: out std_logic);
end TopLevel_DualPort_Ram_XilinxCore;
architecture Arch of TopLevel_DualPort_Ram_XilinxCore is
component Clock_Divider
Port(
ClockIn: in std_logic;
ClockOut: out std_Logic);
end component;
component D4to7
port(
Q: in std_logic_vector (3 downto 0);
Seg: out std_logic_vector (6 downto 0));
end component;
component Scan4Digit
port(
Digit3, Digit2, Digit1, Digit0: in std_logic_vector(6 downto 0);
Clock: in std_logic;
An : out std_logic_vector (3 downto 0);
Ca, Cb, Cc, Cd, Ce, Cf, Cg, Dp: out std_logic);
end component;
-- Dual port RAM generated from Xilinx core generator
component dpram16x4
port (
    addra: IN std_logic_VECTOR(3 downto 0);
    addrb: IN std_logic_VECTOR(3 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dina: IN std_logic_VECTOR(3 downto 0);
    dinb: IN std_logic_VECTOR(3 downto 0);
    douta: OUT std_logic_VECTOR(3 downto 0);
    doutb: OUT std_logic_VECTOR(3 downto 0);
    ena: IN std_logic;
    enb: IN std_logic;
    wea: IN std_logic;
    web: IN std_logic);
end component;
-- Paste Dual port RAM component declaration here
signal iClock: std_logic;
signal iWriteAddress: std_logic_vector (3 downto 0) := (others=>'0');
signal iReadAddress: std_logic_vector (3 downto 0) := (others=>'0');
signal iDigitOut3, iDigitOut2, iDigitOut1, iDigitOut0: std_logic_vector (6 downto 0);
begin
-- Paste the dual-port RAM component instantiation here
-- and Substitute your own instance name and net names
-- Read/Write clock for dual-port RAM is generated fromsystem clock (50MHz)

U1: dpram16x4
port map (
            addra => iWriteAddress,
            addrb => iReadAddress,
            clka => iClock,
            clkb => iClock,
            dina => DataIn,
            dinb => DataIn,
            douta => DataOutA,
            doutb => DataOutB,
            ena => ena,
            enb => enb,
            wea => WenableA,
            web => WenableB);
				
				
U2: Clock_Divider 
	port map(
	ClockIn => SystemClock,
	ClockOut => iClock);

-- Write address for dual-port RAM is generated based on clock signal, iClock,
-- and write address enable signal, WriteAddress
process(iClock)
begin
if iClock'event and iClock='1' then
	if WriteAddress = '1' then
		iWriteAddress <= iWriteAddress + '1';		
	end if;
end if;
end process;

-- Read address for dual-port RAM is generated based on clock signal, iClock,
-- and read address enable signal, ReadAddress
process(iClock)
begin
if iClock'event and iClock='1' then
	if ReadAddress = '1' then
		iReadAddress <= iReadAddress + '1';		
	end if;
end if;
end process;

-- Write address is 7-segment encoded and sent to digit 0 for display
U3: D4to7 port map(
Q => iWriteAddress,
Seg => iDigitOut0);
-- Read address is 7-segment encoded and sent to digit 2 for display
U4: D4to7 port map(
Q => iReadAddress,
Seg => iDigitOut2);

-- '0' is displayed at digit 1 and digit 3
-- because only addresses 0-F are needed for dual-port RAM 16x4
iDigitOut1 <= "0000001";
iDigitOut3 <= "0000001";
-- 7-segment display

U5: Scan4Digit port map(
Digit3 => iDigitOut3,
Digit2 => iDigitOut2,
Digit1 => iDigitOut1,
Digit0 => iDigitOut0,
Clock => SystemClock,
An => An,
Ca => Ca,
Cb => Cb,
Cc => Cc,
Cd => Cd,
Ce => Ce,
Cf => Cf,
Cg => Cg,
Dp => Dp);
end Arch;