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mpdma/pcores/fifo_link_v1_00_a/hdl/vhdl
anal.out
G:/Documents and Settings/hejianbin/My Documents/vhdl/busis.vhd:
genmultcode.cpp
////////////////////////////////////////////
// Automatic Multiplier Generator Tool //
// Generate Multipplyers Code (VHDL) //
// from Script //
////////////////////
tap.vhd
-- D:\DOWNLOADS\JTAG\DESIGN\TAP\TAP.vhd
-- VHDL code created by Xilinx's StateCAD 5.03
-- Fri Nov 24 18:06:22 2006
-- This VHDL code (for use with IEEE compliant tools) was generated using:
tb_adderregister.tbw
version 3
C:/Documents and Settings/People/Desktop/VLSIASS2/EnableAndStart.vhd
EnableAndStart
VHDL
VHDL
TB_ADDERREGISTER.xwv
Comb
50000000
50000000
1000000000
ns
GSR:false
PRLD:false
1000
i2c_timesim.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.26
-- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log i2c.nga i2c_timesim.vhd
-- Input file: i2c.nga
-- Output file: i2c_timesim
i2c_timesim.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.26
-- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log i2c.nga i2c_timesim.vhd
-- Input file: i2c.nga
-- Output file: i2c_timesim
i2c_timesim.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.26
-- Command: -rpw 100 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log i2c.nga i2c_timesim.vhd
-- Input file: i2c.nga
-- Output file: i2c_timesim
hdpdeps.ref
V1 4
FL f:/lqj/1/bulkin/fpga/top.vhdl 2006/10/24.11:23:48
FL F:/lqj/1/BulkOut/FPGA/top.vhdl 2006/11/13.11:10:28
EN work/TOP FL F:/lqj/1/BulkOut/FPGA/top.vhdl PB ieee/STD_LOGIC_1164 \
hdllib.ref
AR mcu behave E:/temp/95144/vhdl/MCU/mcu.vhd sub00/vhpl01 1140425458
EN mcu NULL E:/temp/SPARTAN2/vhdl/Interface/MCU/MCU.vhd sub00/vhpl00 1140866235
AR mcu arch E:/temp/SPARTAN2/vhdl/Interface/MCU/M