tb_adderregister.tbw

Self timed pipelined adder

version 3
C:/Documents and Settings/People/Desktop/VLSIASS2/EnableAndStart.vhd
EnableAndStart
VHDL
VHDL
TB_ADDERREGISTER.xwv
Comb
50000000
50000000
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
Carry_Out_DIFF
Done_DIFF
Out_put_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
Enable
St
Reset
Done
InputA
InputB
Carry_Out
Out_put
SIGNAL_ORDER_END
-X-X-X-