tap.vhd

jtag TAP控制状态机代码 verilog VHDL

--  D:\DOWNLOADS\JTAG\DESIGN\TAP\TAP.vhd
--  VHDL code created by Xilinx's StateCAD 5.03
--  Fri Nov 24 18:06:22 2006

--  This VHDL code (for use with IEEE compliant tools) was generated using: 
--  enumerated state assignment with structured code format.
--  Minimization is enabled,  implied else is enabled, 
--  and outputs are speed optimized.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY TAP IS
	PORT (CLK,TMS,TRST: IN std_logic);
END;

ARCHITECTURE BEHAVIOR OF TAP IS
	TYPE type_sreg IS (CAPTURE_DR,CAPTURE_IR,EXIT1_DR,EXIT1_IR,EXIT2_DR,EXIT2_IR
		,PAUSE_DR,PAUSE_IR,RUN_TEST_IDLE,SELECT_DR_SCAN,SELECT_IR_SCAN,SHIFT_DR,
		SHIFT_IR,TEST_LOGIC_RESET,UPDATE_DR,UPDATE_IR);
	SIGNAL sreg, next_sreg : type_sreg;
BEGIN
	PROCESS (CLK, TRST, next_sreg)
	BEGIN
		IF ( TRST='0' ) THEN
			sreg <= TEST_LOGIC_RESET;
		ELSIF CLK='1' AND CLK'event THEN
			sreg <= next_sreg;
		END IF;
	END PROCESS;

	PROCESS (sreg,TMS)
	BEGIN

		next_sreg<=CAPTURE_DR;

		CASE sreg IS
			WHEN CAPTURE_DR =>
				IF ( TMS='1' ) THEN
					next_sreg<=EXIT1_DR;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=SHIFT_DR;
				END IF;
			WHEN CAPTURE_IR =>
				IF ( TMS='1' ) THEN
					next_sreg<=EXIT1_IR;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=SHIFT_IR;
				END IF;
			WHEN EXIT1_DR =>
				IF ( TMS='1' ) THEN
					next_sreg<=UPDATE_DR;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=PAUSE_DR;
				END IF;
			WHEN EXIT1_IR =>
				IF ( TMS='0' ) THEN
					next_sreg<=PAUSE_IR;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=UPDATE_IR;
				END IF;
			WHEN EXIT2_DR =>
				IF ( TMS='0' ) THEN
					next_sreg<=SHIFT_DR;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=UPDATE_DR;
				END IF;
			WHEN EXIT2_IR =>
				IF ( TMS='1' ) THEN
					next_sreg<=UPDATE_IR;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=SHIFT_IR;
				END IF;
			WHEN PAUSE_DR =>
				IF ( TMS='0' ) THEN
					next_sreg<=PAUSE_DR;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=EXIT2_DR;
				END IF;
			WHEN PAUSE_IR =>
				IF ( TMS='1' ) THEN
					next_sreg<=EXIT2_IR;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=PAUSE_IR;
				END IF;
			WHEN RUN_TEST_IDLE =>
				IF ( TMS='1' ) THEN
					next_sreg<=SELECT_DR_SCAN;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=RUN_TEST_IDLE;
				END IF;
			WHEN SELECT_DR_SCAN =>
				IF ( TMS='1' ) THEN
					next_sreg<=SELECT_IR_SCAN;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=CAPTURE_DR;
				END IF;
			WHEN SELECT_IR_SCAN =>
				IF ( TMS='1' ) THEN
					next_sreg<=TEST_LOGIC_RESET;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=CAPTURE_IR;
				END IF;
			WHEN SHIFT_DR =>
				IF ( TMS='0' ) THEN
					next_sreg<=SHIFT_DR;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=EXIT1_DR;
				END IF;
			WHEN SHIFT_IR =>
				IF ( TMS='1' ) THEN
					next_sreg<=EXIT1_IR;
				END IF;
				IF ( TMS='0' ) THEN
					next_sreg<=SHIFT_IR;
				END IF;
			WHEN TEST_LOGIC_RESET =>
				IF ( TMS='0' ) THEN
					next_sreg<=RUN_TEST_IDLE;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=TEST_LOGIC_RESET;
				END IF;
			WHEN UPDATE_DR =>
				IF ( TMS='0' ) THEN
					next_sreg<=RUN_TEST_IDLE;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=SELECT_DR_SCAN;
				END IF;
			WHEN UPDATE_IR =>
				IF ( TMS='0' ) THEN
					next_sreg<=RUN_TEST_IDLE;
				END IF;
				IF ( TMS='1' ) THEN
					next_sreg<=SELECT_DR_SCAN;
				END IF;
			WHEN OTHERS =>
		END CASE;
	END PROCESS;
END BEHAVIOR;