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sn_ksyms.c
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 200
ddr_sdram_ddr_sdram_vsim.tcl
# ###########################################################################
#
# This script compiles the exmaple_instance and associated testbench
# that matches the DDR_SDRAM MegaCore that
ddr_sdram_ddr_sdram_vsim.tcl
# ###########################################################################
#
# This script compiles the exmaple_instance and associated testbench
# that matches the DDR_SDRAM MegaCore that
fir32a_add.tcl
set_global_assignment -name "VHDL_FILE" "C:/DSP_Biulder_Demo/sin_cos_modem/fir32a.vhd";
set_global_assignment -name "VERILOG_FILE" "C:/DSP_Biulder_Demo/sin_cos_modem/fir32a_st.v";
set_global_assignm
reset_block_wrapper_xst.prj
VHDL proc_sys_reset_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_sys_reset_v1_00_a/hdl/vhdl/upcnt_n.vhd
VHDL proc_sys_reset_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_sys_reset_v1_00_a/
reset_block_wrapper_xst.prj
VHDL proc_sys_reset_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_sys_reset_v1_00_a/hdl/vhdl/upcnt_n.vhd
VHDL proc_sys_reset_v1_00_a g:\EDK\hw\XilinxProcessorIPLib\pcores\proc_sys_reset_v1_00_a/
top_syn.prj
#add_file options
add_file -vhdl "C:/Libero/Synplify/Synplify_85F/lib/proasic/proasic3.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/binary_counter.vhd"
add_file -vhdl "C:/Actelprj/PA3_Demo
stopwatch.prj
verilog work cnt60.vf
vhdl work hex2led.vhd
verilog work dcm1.v
vhdl work decode.vhd
verilog work outs3.vf
verilog work tenths.v
vhdl work STMACH_V.vhd
verilog work stopwatch.vf
top_syn.prj
#add_file options
add_file -vhdl "C:/Libero/Synplify/Synplify_85F/lib/proasic/proasic3.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/binary_counter.vhd"
add_file -vhdl "C:/Actelprj/PA3_Demo
my_axi_ip_xst.prj
vhdl proc_common_v3_00_a "C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\14.2\ISE_DS\EDK/hw/XilinxProce