top_syn.prj

ACTEL A3P StartKit FPGA开发全套文挡（含测试源码）

#add_file options
add_file -vhdl "C:/Libero/Synplify/Synplify_85F/lib/proasic/proasic3.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/binary_counter.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/LED_Flashing.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/count8.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/clockdiv.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/mux2.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/Data_block.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/my_clk_divider.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/Data_to_LCD.vhd"
add_file -vhdl "C:/Actelprj/PA3_DemoBoard_72/hdl/Top.vhd"

#device options
set_option -technology ProASIC3
set_option -part A3P250

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "C:/Actelprj/PA3_DemoBoard_72/synthesis/TOP.edn"