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VHDL 的代码
topdown.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
元件例化与层次设计.txt
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
seg7_m8.cmd
STYFILENAME: mico8.sty
PROJECT: Seg7_M8
WORKING_PATH: "c:/projects/reference/mico8_vhdl/mico8_v2.4b/advanced_ecp6"
MODULE: Seg7_M8
VHDL_FILE_LIST: "C:/Tools/Lattice/ispTOOLS7_0/ispcpld/../cae_libr
dip8_m8.cmd
STYFILENAME: mico8.sty
PROJECT: DIP8_M8
WORKING_PATH: "c:/projects/reference/mico8_vhdl/mico8_v2_4b/block_mico8_ecp6"
MODULE: DIP8_M8
VHDL_FILE_LIST: "C:/Tools/Lattice/ispTOOLS7_0/ispcpld/../cae_l