元件例化与层次设计.txt

4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态 机,元件例化与层次设计,最高优先级编码器

VHDL: Creating a Hierarchical Design

This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd. 
In the top.vhd file, a component for the logic function is declared inside the architecture in which it is instantiated. 
The Component Declaration defines the ports of the lower-level function.
download from: http://www.fpga.com.cn

-----------------------------------------------------------------------------

top.vhd (Top-level file) 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY top IS
      PORT(w_in, x_in, y_in	:IN std_logic;
               clock        :IN std_logic;
               z_out        :OUT std_logic);
END top;

ARCHITECTURE a OF top IS

COMPONENT logic
        PORT(a,b,c    :IN std_logic;
              x       :OUT std_logic);
END COMPONENT;

SIGNAL w_reg, x_reg, y_reg, z_reg	:std_logic;

BEGIN
low_logic       : logic PORT MAP (a => w_reg, b => x_reg, c => y_reg, x => z_reg);

PROCESS(clock)
BEGIN
     IF (clock'event AND clock='1') THEN
         w_reg<=w_in;
         x_reg<=x_in;
         y_reg<=y_in;
         z_out<=z_reg;
    END IF;
END PROCESS;
			
END a;



--------------------------------------------------------------------------------

logic.vhd 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY logic IS
      PORT(a,b,c     : IN std_logic;
             x       : OUT std_logic);
END logic;

ARCHITECTURE a OF logic IS
BEGIN
PROCESS (a,b,c)
BEGIN
     x<=(a and b) or c;
END PROCESS;
END;