top.hpj

Allegro原理图和PCB

<!DOCTYPE SimulationProject SYSTEM "hdl-prj.dtd">
<SimulationProject ProductVersion="8.6c" Logfile="TOP.log" AutoParseProject="1" NameOfComponentToParse="TOP" Keyfile="vhdl.key" Language="vhdl" DelayType="typical" AddTopLevelSignals="0" FileNamesShown="1" HideEmptyLists="1" ShowWatch="1" DumpWatch="0" InteractiveMode="1" ParametersAreWatchable="0" ClearLogBeforeCompile="1" CreateLogFileDuringSim="1" > 
  <FileList>
    <File>F:\Documents\Eval_board\PA3_starter_kit\newboard\A3P_brd\hdl\Top.vhd</File>
  </FileList>
  <DirList>
    <Directory>D:\Libero62\WFL\</Directory>
    <Directory>F:\Documents\Eval_board\PA3_starter_kit\newboard\A3P_brd\hdl</Directory>
  </DirList>
  <LibDirList>
    <Directory>D:\Libero62\WFL\lib\vhd\</Directory>
    <Directory>D:\Libero62\Designer/lib/vtl/95/proasic3.vhd</Directory>
  </LibDirList>
  <LibExtensionList>
    <Extension>.vhd</Extension>
  </LibExtensionList>
</SimulationProject>