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VHDL 的代码
stopwatch_translate.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd
-- Input file: stopwa
stopwatch_translate.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd
-- Input file: stopwa
s59_tw.tbw
version 3
s59.vhdl
s59
VHDL
VHDL
s59_tw.xwv
Clocked
-
-
20000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLK
50000000
50000000
10000000
10000000
0
RISING
CLOCK_LIST_EN
stopwatch_translate.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd
-- Input file: stopwa
stopwatch_translate.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd
-- Input file: stopwa
stopwatch_translate.vhd
-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd
-- Input file: stopwa
ext_ram_lane0_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
sys_ram_lane2_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
uart_rx_stimulus_source_character_source_rom_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li
ext_ram_lane2_module.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
li