ext_ram_lane0_module.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

library std;
use std.textio.all;

entity ext_ram_lane0_module is 
        port (
              -- inputs:
                 signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                 signal rdaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal rdclken : IN STD_LOGIC;
                 signal wraddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
                 signal wrclock : IN STD_LOGIC;
                 signal wren : IN STD_LOGIC;

              -- outputs:
                 signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
              );

end entity ext_ram_lane0_module;


architecture europa of ext_ram_lane0_module is
  component lpm_ram_dp is
GENERIC (
      lpm_rdaddress_control : STRING;
        lpm_indata : STRING;
        lpm_width : NATURAL;
        suppress_memory_conversion_warnings : STRING;
        lpm_file : STRING;
        lpm_outdata : STRING;
        lpm_widthad : NATURAL;
        lpm_hint : STRING;
        lpm_wraddress_control : STRING
      );
    PORT (
    signal q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        signal data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        signal wraddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
        signal wrclock : IN STD_LOGIC;
        signal rdaddress : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
        signal rdclken : IN STD_LOGIC;
        signal wren : IN STD_LOGIC
      );
  end component lpm_ram_dp;
              signal internal_q2 :  STD_LOGIC_VECTOR (7 DOWNTO 0);
              TYPE mem_array is ARRAY( 262143 DOWNTO 0) of STD_LOGIC_VECTOR(7 DOWNTO 0);
              signal memory_has_been_read :  STD_LOGIC;
              signal read_address :  STD_LOGIC_VECTOR (17 DOWNTO 0);

begin

  read_address <= rdaddress;
  lpm_ram_dp_component : lpm_ram_dp
    generic map(
      lpm_rdaddress_control => "UNREGISTERED",
      lpm_indata => "REGISTERED",
      lpm_width => 8,
      suppress_memory_conversion_warnings => "ON",
      lpm_file => "ext_ram_lane0.mif",
      lpm_outdata => "UNREGISTERED",
      lpm_widthad => 18,
      lpm_hint => "USE_EAB=ON",
      lpm_wraddress_control => "REGISTERED"
    )
    port map(
            wraddress => wraddress,
            data => data,
            wrclock => wrclock,
            rdaddress => read_address,
            q => internal_q2,
            rdclken => rdclken,
            wren => wren
    );

  --vhdl renameroo for output signals
  q <= internal_q2;
end europa;