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# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

V3 7 FL D:/Stuffz/VHDL/Test_LCD/LCD_Controller_tbw.ant 2007/07/15.23:25:50 I.24 EN work/LCD_Controller_tbw 1184513154 FL D:/Stuffz/VHDL/Test_LCD/LCD_Controller_tbw.ant \ PB ieee/std_logic_116

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

m255 o dD:\Projects\altera\lpcores\ddr\release\VHDL\V1_0\simulation Ealtcam DP std textio K]Z^fghZ6B=BjnK5NomDT3 DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:A

m255 o dD:\Projects\altera\lpcores\ddr\release\VHDL\V1_0\simulation Ealtcam DP std textio K]Z^fghZ6B=BjnK5NomDT3 DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:A

m255 o dD:\Projects\altera\lpcores\ddr\release\VHDL\V1_0\simulation Ealtcam DP std textio K]Z^fghZ6B=BjnK5NomDT3 DP ieee std_logic_arith XinSYO>L7_n;;dMn;72:52 DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:A

ProjNav -> New -> Test Fixture __projnav/createTF.err # ModelSim : Simulate Behavioral VHDL Model TEST_gate.fdo # ModelSim : Simulate Behavioral VHDL Model vsim.wlf # VHDL : Create Schematic Sym

# VHDL : PDCL (jhdparse) __projnav/pn_correlation_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/fifo_status_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/pn_correlation_fsm_jhdparse_t

# VHDL : PDCL (jhdparse) __projnav/pn_correlation_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/fifo_status_jhdparse_tcl.rsp # VHDL : PDCL (jhdparse) __projnav/pn_correlation_fsm_jhdparse_t