yibutongxin.gfl

用VHDL编写的串口异步通信的例子

ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ModelSim : Simulate Behavioral VHDL Model
TEST_gate.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# VHDL : Create Schematic Symbol
__projnav/tb.rsp
__projnav/vhd2spl.err
# VHDL : View HDL Instantiation Template
__projnav/tb.rsp
yibutongxin.vhi
__projnav/vhd2vhi.err
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
yibutongxin.ngc
yibutongxin.ngr
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
yibutongxin.ngc
yibutongxin.ngr
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
yibutongxin.ngc
yibutongxin.ngr
# Implmentation : Translate (CPLD flow)
__projnav/yibutongxin_edfTOngd_tcl.rsp
yibutongxin.ngd
yibutongxin.bld
yibutongxin_ngdbuild.nav
_ngo/netlist.lst
.untf
yibutongxin_html
yibutongxin.cmd_log
# Implmentation : FitRpt
yibutongxin_html
yibutongxin._hrpt
yibutongxin.cmd_log
# Implmentation : FitRpt
yibutongxin.rpth
# Implmentation : Fit
__projnav/yibutongxin_ngdTOvm6_tcl.rsp
yibutongxin.vm6
yibutongxin.cxt
yibutongxin.blx
yibutongxin.mfd
yibutongxin.rpt
yibutongxin.log
yibutongxin.pnx
yibutongxin.gyd
yibutongxin.xml
yibutongxin_build.xml
yibutongxin.ptf
yibutongxin.bl
errors.xml
tmperr.err
yibutongxin.cmd_log
# Create Timing Constraints
# Create Timing Constraints
# Create Timing Constraints
# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# Implmentation : Translate (CPLD flow)
__projnav/yibutongxin_edfTOngd_tcl.rsp
yibutongxin.ngd
yibutongxin.bld
yibutongxin_ngdbuild.nav
_ngo/netlist.lst
yibutongxin.ucf.untf
yibutongxin_html
yibutongxin.cmd_log
# Create Timing Constraints
# Edit Constraints (Text)
# Implmentation : FitRpt
yibutongxin_html
yibutongxin._hrpt
yibutongxin.cmd_log
# Implmentation : FitRpt
yibutongxin.rpth
# Implmentation : Fit
__projnav/yibutongxin_ngdTOvm6_tcl.rsp
yibutongxin.vm6
yibutongxin.cxt
yibutongxin.blx
yibutongxin.mfd
yibutongxin.rpt
yibutongxin.log
yibutongxin.pnx
yibutongxin.gyd
yibutongxin.xml
yibutongxin_build.xml
yibutongxin.ptf
yibutongxin.bl
errors.xml
tmperr.err
yibutongxin.cmd_log
# Compile HDL Simulation Libraries
compxlib.log
yibutongxin.cxl
yibutongxin.compxlib_log
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
kk_vhd.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Implmentation : FitRpt
yibutongxin_html
yibutongxin._hrpt
yibutongxin.cmd_log
# Implmentation : FitRpt
yibutongxin.rpth
# Implmentation : Fit
__projnav/yibutongxin_ngdTOvm6_tcl.rsp
yibutongxin.vm6
yibutongxin.cxt
yibutongxin.blx
yibutongxin.mfd
yibutongxin.rpt
yibutongxin.log
yibutongxin.pnx
yibutongxin.gyd
yibutongxin.xml
yibutongxin_build.xml
yibutongxin.ptf
yibutongxin.bl
errors.xml
tmperr.err
yibutongxin.cmd_log
# Implmentation : Translate (CPLD flow)
__projnav/yibutongxin_edfTOngd_tcl.rsp
yibutongxin.ngd
yibutongxin.bld
yibutongxin_ngdbuild.nav
_ngo/netlist.lst
yibutongxin.ucf.untf
yibutongxin_html
yibutongxin.cmd_log
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
kkk_bencher.prj
# ProjNav -> New Source -> TBW
kkk.vhw
kkk.ano
kkk.tfw
kkk.ant
# Bencher : Creating project file
kkk_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Launch ModelSim Simulator
yibutongxin.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# Implmentation : FitRpt
yibutongxin_html
yibutongxin._hrpt
yibutongxin.cmd_log
# Implmentation : FitRpt
yibutongxin.rpth
# Implmentation : Fit
__projnav/yibutongxin_ngdTOvm6_tcl.rsp
yibutongxin.vm6
yibutongxin.cxt
yibutongxin.blx
yibutongxin.mfd
yibutongxin.rpt
yibutongxin.log
yibutongxin.pnx
yibutongxin.gyd
yibutongxin.xml
yibutongxin_build.xml
yibutongxin.ptf
yibutongxin.bl
errors.xml
tmperr.err
yibutongxin.cmd_log
# XST (Creating Lso File) : 
yibutongxin.lso
# xst flow : RunXST
yibutongxin.syr
yibutongxin.prj
yibutongxin.sprj
yibutongxin.ana
yibutongxin.stx
yibutongxin.cmd_log
yibutongxin.ngc
yibutongxin.ngr