image.qsf

可以受上位机控制的通过fpga的视频信号发生器程序

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		image_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:04:31  APRIL 30, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name VHDL_FILE rom4.vhd
set_global_assignment -name AHDL_FILE expander.tdf
set_global_assignment -name AHDL_FILE i2cregin.tdf
set_global_assignment -name AHDL_FILE i2cregout.tdf
set_global_assignment -name AHDL_FILE i2cslave.tdf
set_global_assignment -name AHDL_FILE importN7bits.tdf
set_global_assignment -name AHDL_FILE medianfilter.tdf
set_global_assignment -name AHDL_FILE posedge.tdf
set_global_assignment -name SOURCE_FILE ram1.cmp
set_global_assignment -name VHDL_FILE ram1.vhd
set_global_assignment -name SOURCE_FILE rom1.cmp
set_global_assignment -name VHDL_FILE rom1.vhd
set_global_assignment -name VHDL_FILE image.vhd
set_global_assignment -name VHDL_FILE moving_object.vhd
set_global_assignment -name VHDL_FILE moving.vhd
set_global_assignment -name VHDL_FILE shinning.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE image.vwf
set_global_assignment -name VHDL_FILE shiningblock.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name VHDL_FILE rgb.vhd
set_global_assignment -name VHDL_FILE experiment.vhd
set_global_assignment -name VHDL_FILE tri_block.vhd
set_global_assignment -name VHDL_FILE andor.vhd
set_global_assignment -name VHDL_FILE catch.vhd
set_global_assignment -name VHDL_FILE op3.vhd
set_global_assignment -name MIF_FILE ram2.mif
set_global_assignment -name VHDL_FILE op1.vhd
set_global_assignment -name MIF_FILE ram4.mif
set_global_assignment -name MIF_FILE rom1.mif
set_global_assignment -name MIF_FILE rom2.mif
set_global_assignment -name MIF_FILE rom3.mif
set_global_assignment -name MIF_FILE ram1.mif
set_global_assignment -name MIF_FILE ram5.mif
set_global_assignment -name MIF_FILE Ram6.mif
set_global_assignment -name MIF_FILE Ram7.mif
set_global_assignment -name MIF_FILE rom4.mif
set_global_assignment -name MIF_FILE rom5.mif
set_global_assignment -name MIF_FILE rom6.mif
set_global_assignment -name MIF_FILE ram8.mif
set_global_assignment -name MIF_FILE ram9.mif
set_global_assignment -name MIF_FILE ram10.mif

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_J4 -to clk
set_location_assignment PIN_B14 -to clk_out
set_location_assignment PIN_N13 -to de_out
set_location_assignment PIN_F13 -to hs_out
set_location_assignment PIN_G12 -to vs_out
set_location_assignment PIN_G14 -to pixs_out
set_location_assignment PIN_B6 -to out_b_e[0]
set_location_assignment PIN_D2 -to out_b_e[1]
set_location_assignment PIN_E10 -to out_b_e[2]
set_location_assignment PIN_B8 -to out_b_e[3]
set_location_assignment PIN_A8 -to out_b_e[4]
set_location_assignment PIN_D8 -to out_b_e[5]
set_location_assignment PIN_C8 -to out_b_e[6]
set_location_assignment PIN_E8 -to out_b_e[7]
set_location_assignment PIN_E7 -to out_g_e[0]
set_location_assignment PIN_D6 -to out_g_e[1]
set_location_assignment PIN_B9 -to out_g_e[2]
set_location_assignment PIN_A9 -to out_g_e[3]
set_location_assignment PIN_C9 -to out_g_e[4]
set_location_assignment PIN_D9 -to out_g_e[5]
set_location_assignment PIN_D10 -to out_g_e[6]
set_location_assignment PIN_C10 -to out_g_e[7]
set_location_assignment PIN_A7 -to out_r_e[0]
set_location_assignment PIN_C7 -to out_r_e[1]
set_location_assignment PIN_B11 -to out_r_e[2]
set_location_assignment PIN_D12 -to out_r_e[3]
set_location_assignment PIN_E13 -to out_r_e[4]
set_location_assignment PIN_A12 -to out_r_e[5]
set_location_assignment PIN_B12 -to out_r_e[6]
set_location_assignment PIN_C12 -to out_r_e[7]
set_location_assignment PIN_E4 -to out_b_o[0]
set_location_assignment PIN_B15 -to out_b_o[1]
set_location_assignment PIN_A15 -to out_b_o[2]
set_location_assignment PIN_C16 -to out_b_o[3]
set_location_assignment PIN_B16 -to out_b_o[4]
set_location_assignment PIN_A13 -to out_b_o[5]
set_location_assignment PIN_B13 -to out_b_o[6]
set_location_assignment PIN_C13 -to out_b_o[7]
set_location_assignment PIN_D13 -to out_g_o[0]
set_location_assignment PIN_C14 -to out_g_o[1]
set_location_assignment PIN_H6 -to out_g_o[2]
set_location_assignment PIN_D3 -to out_g_o[3]
set_location_assignment PIN_C2 -to out_g_o[4]
set_location_assignment PIN_C3 -to out_g_o[5]
set_location_assignment PIN_D4 -to out_g_o[6]
set_location_assignment PIN_E3 -to out_g_o[7]
set_location_assignment PIN_C15 -to out_r_o[0]
set_location_assignment PIN_D14 -to out_r_o[1]
set_location_assignment PIN_A11 -to out_r_o[3]
set_location_assignment PIN_C11 -to out_r_o[4]
set_location_assignment PIN_D11 -to out_r_o[5]
set_location_assignment PIN_E11 -to out_r_o[6]
set_location_assignment PIN_B10 -to out_r_o[7]
set_location_assignment PIN_A10 -to out_r_o[2]
set_location_assignment PIN_T6 -to scl
set_location_assignment PIN_T4 -to sda
set_location_assignment PIN_F16 -to trigger

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY image

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C20F324C6
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Simulator Assignments
# =====================
set_global_assignment -name GLITCH_INTERVAL 1

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF