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seg47.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
pro3.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
文件列表.txt
文件列表:
FFT变换的IP核的源代码 VHDL~
...........................\FFT的VHDL源代码
...........................\...............\and_gates.vhd
...........................\...............\baseinde
nios_module_fast_output_register.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
en
mhz_counter.vhd
--cyclone32: mhz_counter.vhd
--manual changes are highlighted by '###'
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsig
nios_module_fast_input_register.vhd
library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
en
tba-2470-cpld.gfl
# VHDL : PDCL (jhdparse)
__projnav/tba-2470_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg_2_3_jhdparse_tcl.rsp
# VHDL : PDCL (j
tba-2470-cpld.gfl
# VHDL : PDCL (jhdparse)
__projnav/tba-2470_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/regd_jhdparse_tcl.rsp
# VHDL : PDCL (jhdparse)
__projnav/reg_2_3_jhdparse_tcl.rsp
# VHDL : PDCL (j
expand.cfg
config dummy_root_design;
design newpro001_lib.dummy_root_design:sch_1;
liblist newpro001_lib, new_library;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl
expand.cfg
config dummy_root_design;
design newpro001_lib.dummy_root_design:sch_1;
liblist newpro001_lib, new_library;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl