nios_module_fast_output_register.vhd

来自「ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！」· VHDL 代码 · 共 60 行

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity nios_module_fast_output_register is 
        port (
              -- inputs:
                 signal clk : IN STD_LOGIC;
                 signal clrn : IN STD_LOGIC;
                 signal d : IN STD_LOGIC;
                 signal ena : IN STD_LOGIC;
                 signal prn : IN STD_LOGIC;

              -- outputs:
                 signal q : OUT STD_LOGIC
              );

end entity nios_module_fast_output_register;


architecture europa of nios_module_fast_output_register is
component dffe is 
           port (
                 -- inputs:
                    signal clk : IN STD_LOGIC;
                    signal clrn : IN STD_LOGIC;
                    signal d : IN STD_LOGIC;
                    signal ena : IN STD_LOGIC;
                    signal prn : IN STD_LOGIC;

                 -- outputs:
                    signal q : OUT STD_LOGIC
                 );
end component dffe;

              signal internal_q1 :  STD_LOGIC;
              signal reset_n :  STD_LOGIC;

begin

  my_dffe : dffe
    port map(
      q => internal_q1,
      prn => prn,
      clk => clk,
      ena => ena,
      clrn => clrn,
      d => d
    );


  --vhdl renameroo for output signals
  q <= internal_q1;
end europa;