mhz_counter.vhd

ALTERA的NIOS处理器！文件直接可以打开直接选择器件重新编译！

--cyclone32: mhz_counter.vhd
--manual changes are highlighted by '###'

library altera_vhdl_support;
use altera_vhdl_support.altera_vhdl_support_lib.all;

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mhz_counter is 
        port (
              -- inputs:
                 signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                 signal clk : IN STD_LOGIC;
                 signal cs_n : IN STD_LOGIC;
                 signal reset : IN STD_LOGIC;

              -- outputs:
                 signal dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
              );

end entity mhz_counter;


architecture europa of mhz_counter is
component cnt is 
           port (
                 -- inputs:
                    signal addr : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
                    signal clk : IN STD_LOGIC;
                    signal cs_n : IN STD_LOGIC;
                    signal reset : IN STD_LOGIC;

                 -- outputs:
                    signal dout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
                 );
end component cnt;

              signal internal_dout :  STD_LOGIC_VECTOR (31 DOWNTO 0);

begin

  wrapper : cnt
    port map(
      dout => internal_dout,
      clk => clk,
      reset => reset,
      addr => addr,
      cs_n => cs_n
    );


  --vhdl renameroo for output signals
  dout <= internal_dout;

end europa;