代码搜索结果

sch2vhdl -family spartan2 -flat -suppress -w estrai_cifre.sch estrai_cifre.vhf sch2vhdl -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and Settings/Jernej/Desktop/Termometro_visualiz

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

m255 cModel Technology dD:\quartus_30\quartus\tpi\mgc_oem Edeskew_ram_block DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3 DP ieee vital_timing OBWK>;kUYmkG

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua

文件列表: FFT变换的IP核的源代码 VHDL~ ...........................\FFT的VHDL源代码 ...........................\...............\and_gates.vhd ...........................\...............\baseinde

ProjNav -> New -> Test Fixture __projnav/createTF.err ProjNav -> New -> Test Fixture __projnav/createTF.err # XST (Creating Lso File) : pn_encode.lso # xst flow : RunXST pn_encode.syr pn_enco

project -new #add_file options add_file -vhdl "../rtl/mem_interface_top.vhd" add_file -vhdl "../rtl/mem_interface_top_backend_fifos_0.vhd" add_file -vhdl "../rtl/mem_interface_top_controller_iobs_0

project -new #add_file options add_file -vhdl "../rtl/mem_interface_top.vhd" add_file -vhdl "../rtl/mem_interface_top_addr_gen_0.vhd" add_file -vhdl "../rtl/mem_interface_top_backend_fifos_0.vhd" a

# The MIPS gcc compiler must use the cygwin1.dll that came with the compiler. # The CC_X86 is for compiling tools on your PC. # The GCC_MIPS is for compiling code on the target. # Convert_bin changes