script.tcl

ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）

project -new 
#add_file options
add_file -vhdl "../rtl/mem_interface_top.vhd"
add_file -vhdl "../rtl/mem_interface_top_backend_fifos_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_controller_iobs_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_data_path_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_data_path_iobs_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_data_tap_inc.vhd"
add_file -vhdl "../rtl/mem_interface_top_data_write_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_ddr_controller_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_idelay_ctrl.vhd"
add_file -vhdl "../rtl/mem_interface_top_infrastructure.vhd"
add_file -vhdl "../rtl/mem_interface_top_infrastructure_iobs_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_iobs_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_parameters_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_pattern_compare8.vhd"
add_file -vhdl "../rtl/mem_interface_top_RAM_D_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_rd_data_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_rd_data_fifo_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_rd_wr_addr_fifo_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_tap_ctrl_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_tap_logic_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_top_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_user_interface_0.vhd"
add_file -vhdl "../rtl/mem_interface_top_v4_dm_iob.vhd"
add_file -vhdl "../rtl/mem_interface_top_v4_dq_iob.vhd"
add_file -vhdl "../rtl/mem_interface_top_v4_dqs_iob.vhd"
add_file -vhdl "../rtl/mem_interface_top_wr_data_fifo_16.vhd"
add_file -constraint "../synth/ddr_v4.sdc"
add_file -constraint "../synth/mem_interface_top_dcm_constraints.sdc"
add_file -constraint "../synth/mem_interface_top.sdc"
#implementation: "synth"
impl -add ../synth
#device options
set_option -technology virtex4
set_option -part xc4vsx35
set_option -package ff668
set_option -speed_grade -12
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "mem_interface_top"
#map options
set_option -frequency 200.000
set_option -run_prop_extract 0
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -modular 0
set_option -retiming 1
set_option -no_sequential_opt 0
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 0
#set result format/file last
project -result_file "mem_interface_top.edf"
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 100
set_option -num_startend_points 100
set_option -dup 0
set_option -project_relative_includes 1
#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "synth"
project -run hdl_info_gen -fileorder
project -run
project -save