cpu_mm_manager3.map.qmsg

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 09 11:17:24 2005 " "Info: Processing started: Mon May 09 11:17:24 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cpu_mm_manager3 -c cpu_mm_manager3" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpu_mm_manager3.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file cpu_mm_manager3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 my_own " "Info: Found design unit 1: my_own" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "my_own" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cpu_mm_manager3-CPU_manager_mm_arc3 " "Info: Found design unit 2: cpu_mm_manager3-CPU_manager_mm_arc3" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "cpu_mm_manager3-CPU_manager_mm_arc3" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cpu_mm_manager3 " "Info: Found entity 1: cpu_mm_manager3" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "cpu_mm_manager3" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 17 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "op cpu_mm_manager3.vhd(41) " "Warning: VHDL Signal Declaration warning at cpu_mm_manager3.vhd(41): ignored default value for signal op" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_WARNING_INITIAL_VALUE_FOR_SIGNAL_IS_IGNORED" "statement cpu_mm_manager3.vhd(42) " "Warning: VHDL Signal Declaration warning at cpu_mm_manager3.vhd(42): ignored default value for signal statement" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "bus_wire cpu_mm_manager3.vhd(128) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(128): signal or variable bus_wire may not be assigned a new value in every possible path through the Process Statement. Signal or variable bus_wire holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 128 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cpu_mm_manager3.vhd(196) " "Info: VHDL Case Statement information at cpu_mm_manager3.vhd(196): OTHERS choice is never selected" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 196 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statement cpu_mm_manager3.vhd(209) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(209): signal statement is in statement, but is not in sensitivity list" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 209 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "statement cpu_mm_manager3.vhd(211) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(211): signal statement is in statement, but is not in sensitivity list" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 211 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "alu_out cpu_mm_manager3.vhd(174) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(174): signal or variable alu_out may not be assigned a new value in every possible path through the Process Statement. Signal or variable alu_out holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 174 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cpu_mm_manager3.vhd(951) " "Info: VHDL Case Statement information at cpu_mm_manager3.vhd(951): OTHERS choice is never selected" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 951 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "cpu_mm_manager3.vhd(971) " "Info: VHDL Case Statement information at cpu_mm_manager3.vhd(971): OTHERS choice is never selected" {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 971 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dataout cpu_mm_manager3.vhd(1018) " "Warning: VHDL Process Statement warning at cpu_mm_manager3.vhd(1018): signal or variable dataout may not be assigned a new value in every possible path through the Process Statement. Signal or variable dataout holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" "" "" { Text "E:/2005上学期/数字系统自动设计/实验/VHDL_yuanlai/cpu_mm_manager3.vhd" 1018 0 0 } }  } 0}