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# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

-- Test bench configuration created by tb_gen_vhdl.pl -- Copyright Doulos Ltd -- SD, 10 May 2002 configuration cfg_sine_wave_tb of sine_wave_tb is for bench for uut: sine_wave use en

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

STYFILENAME=getpcmdata.sty PROJECT=getpcmdata ENTRY=Pure VHDL WORKING_PATH=d:/cpld/fpga/getpcmsim MODULE=GetPcm TOP_FILE=getpcm.vhd EDF_FILE_LIST=uartrec.vhd uartsend.vhd baudr.vhd getpcm.vhd pc

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Mon Oct 31 13:04:10 2005 Synplicity VHDL Compiler, version

#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file D:\VHDL_EXERCISE\add_full_n\add_full_n.prj #-- Written on Tue Nov 01 20:52:08 2005 #add_file options add_file -vhdl -lib wor

EN seven_seg NULL D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/seven_seg.vhd sub00/vhpl02 AR clkdll_divide behavioral D:/BJ_xilinx/demo_led/Memec_3SLC_VHDL_ISE63/clkdll_divide.vhd sub00/vhpl01 EN clk

/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2

/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 200

#ifndef OPTFLG_H #define OPTFLG_H /*==================================================================== Copyright 1996, 1997, 2004 Ian Kaplan, Bear Products International, www.bearcave.com. A