pie_code.qsf

pie edcode编码 程序设计

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		pie_code_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C35F672C7
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY pie_code
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:53:18  AUGUST 15, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 6.1
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "IBIS (Signal Integrity)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT IBIS -section_id eda_board_design_signal_integrity
set_global_assignment -name USER_LIBRARIES "F:/program files/altera/61/ip/fir_compiler/lib;F:\\program files\\altera\\61\\ip\\fft-v2.1.1\\lib/;F:\\program files\\altera\\61\\MegaCore\\nco-v2.2.1\\lib/;F:\\program files\\altera\\61\\MegaCore\\fir_compiler-v3.1.0\\lib/"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name VHDL_FILE pie_coding.vhd
set_global_assignment -name VHDL_FILE M_generate.vhd
set_global_assignment -name BDF_FILE pie_code.bdf
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_lib_pkg.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_math_pkg.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_sink.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_source.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/auk_dspip_avalon_streaming_controller.vhd"
set_global_assignment -name VERILOG_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st.v"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_new.vhd"
set_global_assignment -name VHDL_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/fff.vhd"
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ON -entity msft_data
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tdl_da_lc
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_mr
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_en
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity lc_tdl_strat_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_reg_top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_reg_top
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity tsadd_lpm_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity sadd_lpm_reg_top_cen
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF -entity mlu_nd_lc
set_global_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS" -entity fff_st
set_global_assignment -name VERILOG_FILE "F:/program files/altera/61/qdesigns/my_work/pie_code/fff_st_wr.v"