📄 sub_full_n_srr.htm
字号:
<html>
<body><samp><pre>
<!@TC:1130735051>
#Program: Synplify Pro 8.1
#OS: Windows_NT
<a name=compilerReport22>$ Start of Compile
#Mon Oct 31 13:04:10 2005
Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@N: : <a href="d:\vhdl_exercise\sub_full_n\sub_full_n.vhd:1:7:1:17:@N::@XP_MSG">sub_full_n.vhd(1)</a><!@TM:1130735051> | Top entity is set to sub_full_n.
VHDL syntax check successful!
File D:\VHDL_EXERCISE\project1\sub_full.vhd changed - recompiling
@N: : <a href="d:\vhdl_exercise\sub_full_n\sub_full_n.vhd:1:7:1:17:@N::@XP_MSG">sub_full_n.vhd(1)</a><!@TM:1130735051> | Synthesizing work.sub_full_n.sub_full_n
<font color=#A52A2A>@W:<a href="@W:CD453:@XP_HELP">CD453</a> : <a href="d:\vhdl_exercise\sub_full_n\sub_full_n.vhd:21:37:21:45:@W:CD453:@XP_MSG">sub_full_n.vhd(21)</a><!@TM:1130735051> | Index 0 may be out of range</font>
<font color=#A52A2A>@W:<a href="@W:CD453:@XP_HELP">CD453</a> : <a href="d:\vhdl_exercise\sub_full_n\sub_full_n.vhd:29:33:29:38:@W:CD453:@XP_MSG">sub_full_n.vhd(29)</a><!@TM:1130735051> | Index 0 may be out of range</font>
@N: : <a href="d:\vhdl_exercise\sub_full_n\sub_full.vhd:1:7:1:15:@N::@XP_MSG">sub_full.vhd(1)</a><!@TM:1130735051> | Synthesizing work.sub_full.sub_full
Post processing for work.sub_full.sub_full
Post processing for work.sub_full_n.sub_full_n
<font color=#A52A2A>@W:<a href="@W:CL167:@XP_HELP">CL167</a> : <a href="d:\vhdl_exercise\sub_full_n\sub_full_n.vhd:29:0:29:2:@W:CL167:@XP_MSG">sub_full_n.vhd(29)</a><!@TM:1130735051> | Input b_in of instance u3 is floating</font>
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Oct 31 13:04:10 2005
###########################################################[
Version 8.1
Synplicity Proasic Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
<font color=#A52A2A>@W:<a href="@W:BN215:@XP_HELP">BN215</a> : <!@TM:1130735051> | Library scaling: cannot find default operating conditions - failed to scale design</font>
RTL optimization done.
Added 0 Buffers
Added 0 Cells via replication
Writing Analyst data base D:\VHDL_EXERCISE\sub_full_n\rev_3\sub_full_n.srm
Writing EDIF Netlist and constraint files
<a name=timingReport23>##### START OF TIMING REPORT #####[
# Timing Report written on Mon Oct 31 13:04:11 2005
#
Top view: sub_full_n
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1130735051> | This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1130735051> | Clock constraints cover only FF-to-FF paths associated with the clock..
<a name=performanceSummary24>Performance Summary
*******************
Worst slack in design: NA
<a name=interfaceInfo25>Interface Information
*********************
No IO constraint found
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell sub_full_n.sub_full_n
Cell usage:
cell count area count*area
IB33 17 0.0 0.0
XOR2 14 1.0 14.0
OB33PH 9 0.0 0.0
PWR 9 0.0 0.0
GND 9 0.0 0.0
AOI21TTF 5 1.0 5.0
OA21TTF 4 1.0 4.0
OAI21TTF 1 1.0 1.0
NOR2FT 1 1.0 1.0
XOR2FT 1 1.0 1.0
OA21FTT 1 1.0 1.0
OAI21FTT 1 1.0 1.0
----- ----------
TOTAL 72 28.0
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -