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use WORK.LOCAL.all; entity PLA_VHDL is port(IN_VECTOR: BIT_VECTOR(2 downto 0); OUT_VECTOR: out BIT_VECTOR(4 downto 0)); end; architecture BEHAVIOR of PLA_VHDL is constant TABLE: PLA_TABLE

-- Test bench configuration created by tb_gen_vhdl.pl -- Copyright Doulos Ltd -- SD, 10 May 2002 configuration cfg_sine_wave_tb of sine_wave_tb is for bench for uut: sine_wave use en

# xst flow : RunXST rom_asincrona_summary.html # XST (Creating Lso File) : rom_asincrona.lso # xst flow : RunXST rom_asincrona_summary.html # xst flow : RunXST rom_asincrona.syr rom_asincrona

set_global_assignment -name IP_TOOL_NAME "FIR Compiler" set_global_assignment -name IP_TOOL_VERSION "8.1" set_global_assignment -name VHDL_FILE [file join D:/altera/81/ip/altera/fir_compiler/lib "au

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

// PROMGEN: Xilinx Prom Generator G.35 // Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DATE 03/25/06-16:52 SOURCE g:\vijay_kumar\vijay_vhdl6sem_e&elab\vhdl_lab_6seme&e_poly\f

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

Flow report for UDasyncounter Thu Oct 18 13:28:52 2007 Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2006 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu