alu.map.qmsg

这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 10 23:14:09 2009 " "Info: Processing started: Fri Apr 10 23:14:09 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alu -c alu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file ALU.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU-struct " "Info: Found design unit 1: ALU-struct" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ALU " "Info: Found entity 1: ALU" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ALU " "Info: Elaborating entity \"ALU\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(105) " "Info: VHDL Case Statement information at ALU.VHD(105): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 105 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(110) " "Info: VHDL Case Statement information at ALU.VHD(110): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 110 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(115) " "Info: VHDL Case Statement information at ALU.VHD(115): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 115 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(126) " "Info: VHDL Case Statement information at ALU.VHD(126): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 126 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(131) " "Info: VHDL Case Statement information at ALU.VHD(131): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 131 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(136) " "Info: VHDL Case Statement information at ALU.VHD(136): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 136 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(147) " "Info: VHDL Case Statement information at ALU.VHD(147): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 147 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(152) " "Info: VHDL Case Statement information at ALU.VHD(152): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 152 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(157) " "Info: VHDL Case Statement information at ALU.VHD(157): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 157 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(168) " "Info: VHDL Case Statement information at ALU.VHD(168): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 168 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(173) " "Info: VHDL Case Statement information at ALU.VHD(173): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 173 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(178) " "Info: VHDL Case Statement information at ALU.VHD(178): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 178 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(189) " "Info: VHDL Case Statement information at ALU.VHD(189): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 189 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(194) " "Info: VHDL Case Statement information at ALU.VHD(194): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 194 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(199) " "Info: VHDL Case Statement information at ALU.VHD(199): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 199 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(210) " "Info: VHDL Case Statement information at ALU.VHD(210): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 210 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(215) " "Info: VHDL Case Statement information at ALU.VHD(215): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 215 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(220) " "Info: VHDL Case Statement information at ALU.VHD(220): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 220 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "ALU.VHD(254) " "Info: VHDL Case Statement information at ALU.VHD(254): OTHERS choice is never selected" {  } { { "ALU.VHD" "" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 254 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "g:/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_add_sub:ALU_ADDER " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_add_sub:ALU_ADDER\"" {  } { { "ALU.VHD" "ALU_ADDER" { Text "G:/组成实验/1.8 运算器部件实验：算术逻辑运算单元/ALU.VHD" 82 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "g:/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore lpm_add_sub:ALU_ADDER\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"lpm_add_sub:ALU_ADDER\|addcore:adder\"" {  } { { "lpm_add_sub.tdf" "adder" { Text "g:/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "g:/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_add_sub:ALU_ADDER\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_add_sub:ALU_ADDER\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "g:/quartus50/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer lpm_add_sub:ALU_ADDER\|addcore:adder\|a_csnbuffer:result_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"lpm_add_sub:ALU_ADDER\|addcore:adder\|a_csnbuffer:result_node\"" {  } { { "addcore.tdf" "result_node" { Text "g:/quartus50/libraries/megafunctions/addcore.tdf" 120 6 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "g:/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_add_sub:ALU_ADDER\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_add_sub:ALU_ADDER\|altshift:result_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "result_ext_latency_ffs" { Text "g:/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift lpm_add_sub:ALU_ADDER\|altshift:carry_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"lpm_add_sub:ALU_ADDER\|altshift:carry_ext_latency_ffs\"" {  } { { "lpm_add_sub.tdf" "carry_ext_latency_ffs" { Text "g:/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } }  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "2 " "Info: Ignored 2 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "2 " "Info: Ignored 2 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IFTM_CARRY_SINGLE_TO_DOUBLE" "1 " "Info: Converted 1 single input CARRY primitives to CARRY_SUM primitives" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "193 " "Info: Implemented 193 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "20 " "Info: Implemented 20 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "161 " "Info: Implemented 161 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 10 23:14:12 2009 " "Info: Processing ended: Fri Apr 10 23:14:12 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}