pla.vhd

design compile synthesis user guide

use WORK.LOCAL.all;

entity PLA_VHDL is
  port(IN_VECTOR: BIT_VECTOR(2 downto 0);
       OUT_VECTOR: out BIT_VECTOR(4 downto 0));
end;

architecture BEHAVIOR of PLA_VHDL is
  constant TABLE: PLA_TABLE := PLA_TABLE'(
       PLA_ROW'("--- 10000"),
       PLA_ROW'("-1- 01000"),
       PLA_ROW'("0-0 00101"),
       PLA_ROW'("-1- 00101"),
       PLA_ROW'("1-1 00101"),
       PLA_ROW'("-1- 00010"));

begin
  OUT_VECTOR <= PLA(IN_VECTOR, TABLE);
end BEHAVIOR;