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#-- Synplicity, Inc. #-- Version Synplify Pro 8.1 #-- Project file D:\VHDL_EXERCISE\add_full_n\add_full_n.prd #-- Written on Tue Nov 01 20:52:09 2005 # ### Watch Implementation type ### # wat

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Tue Nov 01 17:53:25 2005 Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synplic

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Tue Nov 01 21:08:53 2005 Synplicity VHDL Compiler, versio

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Tue Nov 01 17:53:25 2005 Synplicity VHDL Compiler, version

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

Analysis & Synthesis report for test Fri Sep 21 20:01:12 2007 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal No

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

set_global_assignment -name FAMILY Cyclone set_global_assignment -name DEVICE AUTO set_global_assignment -name TOP_LEVEL_ENTITY sdcard_spi set_global_assignment -name DO_MIN_ANALYSIS OFF set_globa

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I