lcd_success.map.qmsg

基于DE2实验板

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 28 17:45:37 2008 " "Info: Processing started: Mon Apr 28 17:45:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_success -c lcd_success " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_success -c lcd_success" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LCD-Behavioral " "Info: Found design unit 1: LCD-Behavioral" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 18 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LCD " "Info: Found entity 1: LCD" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd " "Info: Elaborating entity \"lcd\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b lcd.vhd(42) " "Warning (10492): VHDL Process Statement warning at lcd.vhd(42): signal \"b\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 42 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Reset lcd.vhd(68) " "Warning (10492): VHDL Process Statement warning at lcd.vhd(68): signal \"Reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[5\]~reg0 data\[4\]~reg0 " "Info: Duplicate register \"data\[5\]~reg0\" merged to single register \"data\[4\]~reg0\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|LCD\|state 4 " "Info: State machine \"\|LCD\|state\" contains 4 states" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 26 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|LCD\|state " "Info: Selected Auto state machine encoding method for state machine \"\|LCD\|state\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 26 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|LCD\|state " "Info: Encoding result for state machine \"\|LCD\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s4 " "Info: Encoded state bit \"state.s4\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s3 " "Info: Encoded state bit \"state.s3\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s2 " "Info: Encoded state bit \"state.s2\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s1 " "Info: Encoded state bit \"state.s1\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD\|state.s1 0000 " "Info: State \"\|LCD\|state.s1\" uses code string \"0000\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD\|state.s2 0011 " "Info: State \"\|LCD\|state.s2\" uses code string \"0011\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD\|state.s3 0101 " "Info: State \"\|LCD\|state.s3\" uses code string \"0101\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD\|state.s4 1001 " "Info: State \"\|LCD\|state.s4\" uses code string \"1001\"" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 68 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 26 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "rw GND " "Warning: Pin \"rw\" stuck at GND" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_on VCC " "Warning: Pin \"lcd_on\" stuck at VCC" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_blon VCC " "Warning: Pin \"lcd_blon\" stuck at VCC" {  } { { "lcd.vhd" "" { Text "E:/FPGA/VHDL_Lab/lcd_success/lcd.vhd" 11 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "79 " "Info: Implemented 79 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 28 17:45:39 2008 " "Info: Processing ended: Mon Apr 28 17:45:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}