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VHDL 的代码
work.tag_mem_tst.prj
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file e:/3/tag_mem\work.tag_mem_tst.prj
#-- Written on Fri Dec 19 12:32:46 2008
#device options
set_option -technology LATTIC
tri_s8_1.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
tri_s8.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
dds.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
alarm_clock.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
dds_top_quartus.tcl
############################################################################################
##
## DSP Builder (Version 7.0)
## Quartus II development tool and MATLAB/Simulink Interface
##
## L
cnt-combin.vhd
entity COUNT_COMB_VHDL is
port(DATA: in BIT_VECTOR(7 downto 0);
COUNT: out INTEGER range 0 to 8;
ERROR: out BOOLEAN);
end;
architecture BEHAVIOR of COUNT_COMB_VHDL is
begin
proces
top.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
isim.hdlsourcefiles
L:/H.39/rtf/vhdl/src/simprims/simprim_VITAL.vhd
E:/DEMO_FPGA/digital_clk_timesim.vhd
E:/DEMO_FPGA/dfgf.timesim_vhw
second.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu