cnt-combin.vhd

design compile synthesis user guide

entity COUNT_COMB_VHDL is
  port(DATA:  in  BIT_VECTOR(7 downto 0);
       COUNT: out INTEGER range 0 to 8;
       ERROR: out BOOLEAN);
end;

architecture BEHAVIOR of COUNT_COMB_VHDL is
begin
  process(DATA)
    variable TEMP_COUNT : INTEGER range 0 to 8;
    variable SEEN_ZERO, SEEN_TRAILING : BOOLEAN;
  begin
    ERROR <= FALSE;
    SEEN_ZERO := FALSE;
    SEEN_TRAILING := FALSE;
    TEMP_COUNT := 0;
    for I in 0 to 7 loop
      if (SEEN_TRAILING and DATA(I) = '0') then
        TEMP_COUNT := 0;
        ERROR <= TRUE;
        exit;
      elsif (SEEN_ZERO and DATA(I) = '1') then
        SEEN_TRAILING := TRUE;
      elsif (DATA(I) = '0') then
        SEEN_ZERO := TRUE;
        TEMP_COUNT := TEMP_COUNT + 1;
      end if;
    end loop;

    COUNT <= TEMP_COUNT;
  end process;

end BEHAVIOR;