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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pmath_complex DP work math_real zjAF7SKfg_RPI0GT^n1N`1 31 b1 M1 work math_real OL;C;6.2b;35 OP;C;6.2b;35 d. F$MODEL_

[Library] others = $MODEL_TECH/../modelsim.ini proasic3 = $MODEL_TECH/../actel/vlog/proasic3 syncad_vhdl_lib = E:\Libero\Designer/lib/actel/syncad_vhdl_lib [vcom] VHDL93 = 1

[Library] others = $MODEL_TECH/../modelsim.ini proasic3 = $MODEL_TECH/../actel/vlog/proasic3 syncad_vhdl_lib = D:\Actel\Libero7.3\Designer/lib/actel/syncad_vhdl_lib [vcom] VHD

# Copyright (C) 1991-2004 Altera Corporation # Any megafunction design, and related netlist (encrypted or decrypted), # support information, device programming or simulation file, and any oth