viterbi_node_sync.qsf

一个完整的viterbi编码程序

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		viterbi_node_sync_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "4.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:19:40  OCTOBER 14, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION "4.1 SP2"
set_global_assignment -name VHDL_FILE ../source/ber_node_sync.vhd
set_global_assignment -name VHDL_FILE ../source/ber_threshold.vhd
set_global_assignment -name VHDL_FILE ../source/mux_2d.vhd
set_global_assignment -name VHDL_FILE ../source/rotate_node_sync.vhd
set_global_assignment -name VHDL_FILE ../source/viterbi_BER.vhd
set_global_assignment -name VHDL_FILE ../source/viterbi_node_sync.vhd
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/vi_interface.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/vi_functions.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/LPM_pack.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_vit_var_enc_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_vit_var_enc_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_add_tre_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_add_tre_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_sel_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_sel_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_met_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_met_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_sur_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_sur_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_acs_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_acs_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_ber_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_ber_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_bmp_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_bmp_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_trb_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_trb_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_top_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_hyb_top_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_ber_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_bmp_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_trb_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_ber_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_trb_atl_arc_mem.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_bmp_atl_arc_rtl.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_top_atl_ent.vhd"
set_global_assignment -name VHDL_FILE "../../../software/altera/megacore/viterbi-v4.1.0/lib/auk_vit_par_top_atl_arc_rtl.vhd"

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY viterbi_node_sync
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name USER_LIBRARIES "C:/software/altera/megacore/viterbi-v4.1.0/lib;"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE AUTO