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myled.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
hamming.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
tbench_armcache.vhd
-- $(lic)
-- $(help_generic)
-- $(help_local)
library ieee;
use ieee.std_logic_1164.all;
use work.int.all;
use work.memdef.all;
use work.corelib.all;
use work.arm_comp.all;
use work.arm
2sn7485.mgf
V 000038 40 1803 1047633583333 e_and2
SYMB0100
HEADER
{
VARIABLES
{
#FUB=""
#HDL_ENTRIES="library STD;\\nuse STD.STANDARD;"
#LANGUAGE="VHDL"
#MODIFIED="943515636"
}
}
PAGE ""
{
memory_example.adf
[Project]
Current Flow=Multivendor
VCS=0
version=1
Current Config=compile
[Configurations]
compile=memory_example
[$LibMap$]
example=.
memory_example=.
[Settings]
FLOW_TYPE=HDL
LANGU
bit_add.bld
Release 6.3i - ngdbuild G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -intstyle ise -dd
g:\vijay_kumar\vijay_vhdl6sem_e&elab\vhdl_lab_6seme&e_poly\fpga_progr
bit_add.vhdsim_map
bit_add.vhdsim_map -- generated only for ProjNav status tracking
Simulation Model Target: Generic_VHDL
timer.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
manqiesite.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any