代码搜索结果

read -format vhdl verilog/new/ALARM_BLOCK.vhd read -format vhdl verilog/new/ALARM_SM_2.vhd read -format vhdl verilog/new/CLOCK_GEN.vhd read -format vhdl verilog/new/COMPARATOR.vhd read -format vhdl ve

sch2vhdl -intstyle ise -family spartan2e -flat -suppress -w fifo12bit_2k.sch fifo12bit_2k.vhf xst -intstyle ise -ifn __projnav/fifo12bit_2k.xst -ofn fifo12bit_2k.syr ngdbuild -intstyle ise -dd "d:\2

; -- modelsim script - can be adapted for other simulators ; -- vcom -work DFT $misr_vhdl/ml_lfsr.vhd vcom -work DFT $misr_vhdl/sig_reg.vhd vcom -work DFT $misr_vhdl/sisr.vhd vcom -work DFT $m

V1 4 FL F:/7-segment/ex3.vhdl 2009/04/09.13:08:54 EN work/EX3 FL F:/7-segment/ex3.vhdl PB ieee/STD_LOGIC_1164 \ PB ieee/STD_LOGIC_ARITH PB ieee/STD_LOGIC_UNSIGNED AR work/EX3/BEH

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

can_top.vhdsim_xlate -- generated only for ProjNav status tracking Simulation Model Target: Generic_VHDL

Release 7.1.01i - netgen H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -intstyle ise -s 6 -pcf digital_clk.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt

Release 7.1.01i - netgen H.39 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Command Line: netgen -intstyle ise -s 6 -pcf digital_clk.pcf -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt