digital_clk.par_nlf

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - netgen H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 6 -pcf digital_clk.pcf -rpw 100 -tpw 0
-ar Structure -xon true -w -ofmt vhdl -sim digital_clk.ncd
digital_clk_timesim.vhd  

Read and Annotate design 'digital_clk.ncd' ...
Loading device for application Rf_Device from file '2s100e.nph' in environment
E:/Program/EDA/Xilinx.
   "digital_clk" is an NCD, version 3.1, device xc2s100e, package pq208, speed
-6
Loading constraints from 'digital_clk.pcf'...
The speed grade (-6) differs from the speed grade specified in the .ncd file
(-6).
The number of routable networks is 58
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'digital_clk_timesim.vhd' ...
Writing VHDL SDF file 'digital_clk_timesim.sdf' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 59476 kilobytes