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#-- Synplicity, Inc. #-- Version 6.0 #-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj #-- Written on Fri Jun 30 17:01:13 2000 #add_file opti

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

--------------------------------------------------------------------------- -- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV, -- the 'Entity Architecture Schematics Editor for VHDL' tool

#-- Synplicity, Inc. #-- Version 6.2.4 #-- Project file mc8051_core.prj #-- Written on Fri Aug 24 19:26:03 2001 #add_file options add_file -vhdl -lib work "../vhdl/mc8051_p.vhd" add_file -vhdl -lib

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni