e10281_ts.vhd

来自「TCM解码」· VHDL 代码 · 共 38 行

---------------------------------------------------------------------------
-- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV,
-- the 'Entity Architecture Schematics Editor for VHDL' tool.
--
---------------------------------------------------------------------------

---------------------------------------------------------------------------
-- Entity declaration of 'd10281_ts'.
---------------------------------------------------------------------------
-- Drawing number       : D10281
-- Drawing description  : Viterbi decoder core
-- 
-- -------------------------------------------------------------
-- This ENTITY is automatically generated by EASE - do not edit.
-- -------------------------------------------------------------

LIBRARY ieee, work ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
USE work.pfec.ALL ;
USE work.d10281_pack.ALL ;

ENTITY d10281_ts IS
  PORT(
    reset_n         : IN     std_logic ;
    clk_ts          : IN     std_logic ;
    field_sync      : IN     std_logic ;
    viterbi_init    : IN     std_logic;
    data_en         : IN     std_logic ;
    data_in         : IN     std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
    data_valid      : OUT    std_logic ;
    data_out        : OUT    std_logic_vector( INPUT_WIDTH-1 DOWNTO 0 ) ;
    trellis_sel     : OUT    std_logic_vector( 3 DOWNTO 0 );
    trellis_count   : OUT    std_logic_vector( 3 DOWNTO 0 ) 
     ) ;
END  d10281_ts ;