speaker.fit.qmsg

用VHDL语言仿真音乐设计 用VHDL语言仿真音乐设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 26 20:05:14 2007 " "Info: Processing started: Mon Nov 26 20:05:14 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off speaker -c speaker " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off speaker -c speaker" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "speaker EP1C3T144C6 " "Info: Selected device EP1C3T144C6 for design \"speaker\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C6 " "Info: Device EP1C6T144C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk8HZ Global clock in PIN 17 " "Info: Automatically promoted signal \"clk8HZ\" to use Global clock in PIN 17" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/songer.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk12MHZ Global clock in PIN 92 " "Info: Automatically promoted signal \"clk12MHZ\" to use Global clock in PIN 92" {  } { { "songer.vhd" "" { Text "D:/eda设计/VHDL/音乐演奏/songer.vhd" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "speaker:u3\|LessThan~40 Global clock " "Info: Automatically promoted signal \"speaker:u3\|LessThan~40\" to use Global clock" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "speaker:u3\|LessThan~40" } } } } { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { speaker:u3|LessThan~40 } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/音乐演奏/speaker.fld" "" { Floorplan "D:/eda设计/VHDL/音乐演奏/speaker.fld" "" "" { speaker:u3|LessThan~40 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "tonetaba:u2\|Mux~303 Global clock " "Info: Automatically promoted signal \"tonetaba:u2\|Mux~303\" to use Global clock" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "tonetaba:u2\|Mux~303" } } } } { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { tonetaba:u2|Mux~303 } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/音乐演奏/speaker.fld" "" { Floorplan "D:/eda设计/VHDL/音乐演奏/speaker.fld" "" "" { tonetaba:u2|Mux~303 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "notetabs:u1\|reduce_nor~0 Global clock " "Info: Automatically promoted signal \"notetabs:u1\|reduce_nor~0\" to use Global clock" {  } { { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "notetabs:u1\|reduce_nor~0" } } } } { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { notetabs:u1|reduce_nor~0 } "NODE_NAME" } "" } } { "D:/eda设计/VHDL/音乐演奏/speaker.fld" "" { Floorplan "D:/eda设计/VHDL/音乐演奏/speaker.fld" "" "" { notetabs:u1|reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.323 ns memory memory " "Info: Estimated most critical path is memory to memory delay of 3.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_e1q:auto_generated\|ram_block1a1~porta_address_reg0 1 MEM M4K_X13_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_e1q:auto_generated\|ram_block1a1~porta_address_reg0'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|ram_block1a1~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_e1q.tdf" "" { Text "D:/eda设计/VHDL/音乐演奏/db/altsyncram_e1q.tdf" 60 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.323 ns) 3.323 ns notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_e1q:auto_generated\|q_a\[1\] 2 MEM M4K_X13_Y8 13 " "Info: 2: + IC(0.000 ns) + CELL(3.323 ns) = 3.323 ns; Loc. = M4K_X13_Y8; Fanout = 13; MEM Node = 'notetabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_e1q:auto_generated\|q_a\[1\]'" {  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|ram_block1a1~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|q_a[1] } "NODE_NAME" } "" } } { "db/altsyncram_e1q.tdf" "" { Text "D:/eda设计/VHDL/音乐演奏/db/altsyncram_e1q.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.323 ns 100.00 % " "Info: Total cell delay = 3.323 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" "" { Report "D:/eda设计/VHDL/音乐演奏/db/speaker_cmp.qrpt" Compiler "speaker" "UNKNOWN" "V1" "D:/eda设计/VHDL/音乐演奏/db/speaker.quartus_db" { Floorplan "D:/eda设计/VHDL/音乐演奏/" "" "3.323 ns" { notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|ram_block1a1~porta_address_reg0 notetabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_e1q:auto_generated|q_a[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 26 20:05:23 2007 " "Info: Processing ended: Mon Nov 26 20:05:23 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}