代码搜索结果

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua

m255 cModel Technology Builtin Library 13 dD:\qa\patch6_2\nightly\master\modeltech Pstandard OL;C;6.2b;35 31 OP;C;6.2b;35 d. F$MODEL_TECH/../vhdl_src/std/standard.vhd l0 L8 V9SL6g`:IK^4S07MiOU]DY2 OE

# # # # Created by Synplify VHDL Compiler version 3.2.0, Build 094R from Synplicity, Inc. # Copyright 1994-2004 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Sun Dec 03 1

@E @ # # # # Created by Synplify VHDL Compiler version 1.0, Build 157R from Synplicity, Inc. # Copyright 1994-2007 Synplicity, Inc. , All rights reserved. # Synthesis Netlist written on Wed Ju

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Tue Nov 01 20:52:34 2005 Synplicity VHDL Compiler, version

@TM:1130734042 @W: BN215 :"":0:0:0:-1|Library scaling: cannot find default operating conditions - failed to scale design @N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Ple

###########################################################[ Version 8.1 Synplicity Proasic Technology Mapper, Version 8.1.0, Build 539R, Built May 6 2005 Copyright (C) 1994-2005, Synplicity Inc.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ram.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.