addr_select.srs

一个组合逻辑实例,完成地址选择,读写信号产生等时序

#
#
#
# Created by Synplify VHDL Compiler version 3.2.0, Build 094R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sun Dec 03 17:53:39 2006
#
#
#OPTIONS:"|-top|ADDR_SELECT|-autosm|-fid2|-sharing|on|-encrypt|-dfltencoding|sequential|-ui|-lite|-ram|-ignore_undefined_lib|-ll|2000|-lib|work"
#CUR:"C:\\ISPTOOLS5_1\\SYNPBASE\\bin\\c_vhdl.exe":1128060544
#CUR:"C:\\ISPTOOLS5_1\\SYNPBASE\\lib\\vhd\\location.map":1126147214
#CUR:"C:\\ISPTOOLS5_1\\SYNPBASE\\lib\\vhd\\std.vhd":1111509928
#CUR:"C:\\ISPTOOLS5_1\\SYNPBASE\\lib\\vhd\\std.vhd":1111509928
#CUR:"C:\\gal_300f\\addr_select.vhd":1164953804
#CUR:"C:\\gal_300f\\addr_select.vhd":1164953804
#CUR:"C:\\ISPTOOLS5_1\\SYNPBASE\\lib\\vhd\\std1164.vhd":927285456
#CUR:"C:\\ISPTOOLS5_1\\SYNPBASE\\lib\\vhd\\std1164.vhd":927285456
f "C:\ISPTOOLS5_1\SYNPBASE\lib\vhd\std.vhd"; # file 0
af .is_vhdl 1;
f "C:\gal_300f\addr_select.vhd"; # file 1
af .is_vhdl 1;
f "C:\ISPTOOLS5_1\SYNPBASE\lib\vhd\std1164.vhd"; # file 2
af .is_vhdl 1;
@E
@ 
ftell;
@E@MR@c4::c(::R4(I	FsR7q7) _1pa BRELCNFPHs;ND
RNP3PH#ER8D4N;
PHR3#E_P84DR;P
NR$3#Ml_VN"bRI	FsRB\":o\\NdD_j\jV\8N8sC_#D0CO38PE\""
;



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9;
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b@:@46j:4:46:jMRHPMRk4r_N.9:jR4kM_.Nr:Rj9N:r.j
9;b@R@j::44::4.sR0k0CRsRkC0Csk;R
b@:@j4::44R:.V#NDCNRVDR#CV#NDCb;
R4@@::4ccc:4:R4cNPM8RR#g#NgRrRj9k_M4N9r4R4kM_.Nr9b;
R4@@::46c6:4:R4cNPM8Rj#4Rj#4R4kM_jNr9rRN4k9RMN4_r;.9
@bR@44:n::c44n:cMRN8#PR4#4R4k4RMN4_rRj9k_M4N9r4R.Nr9C;
;