sub_full_n.ta

该程序实现的N位全减器

###########################################################[
Version 8.1
Synplicity Proasic Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading constraint file: D:\VHDL_EXERCISE\project1\rev_3\sub_full_n.rpt
Adding property syn_ta_max_display_worst_paths, value 5 to view:work.sub_full_n(sub_full_n)


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Oct 31 12:48:28 2005
#


Top view:               sub_full_n
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA
BLogParam: No file to write into.






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

Writing Analyst data base D:\VHDL_EXERCISE\project1\rev_3\sub_full_n_ta.srm
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]