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# Xilinx CORE Generator 6.1i # User = 刘韬 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga\coregen.log # bu

# Bencher : Creating project file tb_uart_bencher.prj # ProjNav -> New Source -> TBW tb_uart.vhw tb_uart.ano tb_uart.tfw tb_uart.ant # Bencher : Creating project file tb_uart_bencher.prj # Pr

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_dec.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_rom.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ctr.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_alu.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

analyze -format vhdl i8051_lib.vhd analyze -format vhdl i8051_ram.vhd vhdlout_architecture_name = "SYN" vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith.all", "LSI_10K.COMPONENTS.

set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "XFFT.v"] set_global_assignment -name VHDL_FILE [file join D:/altera/72/ip/fft/lib "fft_pack_fft_72.vhd"] set_global_assignme