uart01.gfl

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

# Bencher : Creating project file
tb_uart_bencher.prj
# ProjNav -> New Source -> TBW
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# Bencher : Creating project file
tb_uart_bencher.prj
# ProjNav -> New Source -> TBW
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# xst flow : RunXST
top_summary.html
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
# XST (Creating Lso File) : 
top.lso
# xst flow : RunXST
top_summary.html
# xst flow : RunXST
top.syr
top.prj
top.sprj
top.ana
top.stx
top.cmd_log
top.ngc
top.ngr
# Bencher : Creating project file
tb_uart_bencher.prj
# ProjNav -> New Source -> TBW
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# xst flow : RunXST
top_summary.html
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
tb_uart_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
tb_uart_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
tb_uart.vhw
tb_uart.ano
tb_uart.tfw
tb_uart.ant
# ModelSim : Simulate Behavioral VHDL Model
tb_uart.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf