代码搜索：VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
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rpt nd41.rpt
Project Information d:\vhdl_ex\nd41.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 11/11/2003 14:42:24
Copyright (C) 1988-2002 Al
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log coregen.log
# Xilinx CORE Generator 6.1i
# User = 刘韬
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log
# busformat=BusFormatAn
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qsf a6850.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
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pl hierarchy.pl
#! /bin/perl -sw
####################################################
# Copyright (C) 2000 Greg London
# All Rights Reserved.
####################################################
use Hardware::Vhdl:
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v2 nand.v2
entity NAND is
port(in2, in1 : in bit;
out : out bit);
end NAND;
arhitecture VL2VHDL of NAND is
begin
process begin
loop
out
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qsf alu.qsf
# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any oth
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qmsg proj.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
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tlg ddr_sdram.tlg
Synthesizing work.ddr_sdram.rtl
@W:"d:\projects\altera\lpcores\ddr\release\vhdl\v1_0\source\ddr_sdram.vhd":131:14:131:16|Port direction mismatch between component and entity
Synthesizing work.pll1.s
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doc 8.9 ask调制与解调vhdl程序及仿真.doc
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