a6850.qsf

a6850 异步通讯接口

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:26:46  NOVEMBER 20, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 4.0
set_global_assignment -name VHDL_FILE BRKMUX.VHD
set_global_assignment -name VHDL_FILE BUS_CNTL.VHD
set_global_assignment -name VHDL_FILE CNTL_REG.VHD
set_global_assignment -name VHDL_FILE DATACNT.VHD
set_global_assignment -name VHDL_FILE DATAMUX.VHD
set_global_assignment -name VHDL_FILE DATCOUNT.VHD
set_global_assignment -name VHDL_FILE FRAMERR.VHD
set_global_assignment -name VHDL_FILE MUX.VHD
set_global_assignment -name VHDL_FILE PAR_TREE.VHD
set_global_assignment -name VHDL_FILE PARGEN.VHD
set_global_assignment -name VHDL_FILE RCV_REG.VHD
set_global_assignment -name VHDL_FILE RX_STSRG.VHD
set_global_assignment -name VHDL_FILE RXCNTL.VHD
set_global_assignment -name VHDL_FILE RXCNTLSM.VHD
set_global_assignment -name VHDL_FILE RXCOUNT.VHD
set_global_assignment -name VHDL_FILE RXSHFTRG.VHD
set_global_assignment -name VHDL_FILE SRPARGEN.VHD
set_global_assignment -name VHDL_FILE STSRG.VHD
set_global_assignment -name VHDL_FILE TCNTL.VHD
set_global_assignment -name VHDL_FILE TRANSM.VHD
set_global_assignment -name VHDL_FILE TSHFTRG.VHD
set_global_assignment -name VHDL_FILE TX_STSRG.VHD
set_global_assignment -name VHDL_FILE TXCLKCNT.VHD
set_global_assignment -name VHDL_FILE XMIT_REG.VHD
set_global_assignment -name VHDL_FILE A6850.vhd

# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"

# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FAMILY Stratix
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<NONE>"
set_global_assignment -name TOP_LEVEL_ENTITY A6850

# Fitter Assignments
# ==================
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name DEVICE EP1S25F780C6

# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50
set_global_assignment -name RUN_ALL_TIMING_ANALYSES OFF
set_global_assignment -name RUN_TIMING_ANALYSES ON

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_SIMULATION_TOOL "<NONE>"

# Assembler Assignments
# =====================
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2