nand.v2

来自「將Verilog設計轉成VHDL設計的程式」· V2 代码 · 共 13 行

entity NAND is
port(in2, in1 : in bit;
     out : out bit);
end NAND;

arhitecture VL2VHDL of NAND is
begin
process begin
loop
   out <=  not (in1 and in2);
end loop;
end process;
end VL2VHDL;