代码搜索：VHDL

找到约 10,000 项符合「VHDL」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/210234/15203210

lfp yingjiao.lfp

# begin LFP file E:\VHDL\past\pingche\yingjiao.lfp designfile pingche.ngd IO_GROUP "wx" ; IO_GROUP "seg" ; NET "wx" IO_GROUP="wx" ; NET "wx" IO_GROUP="wx" ; NET "wx" IO_GROUP="wx"
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www.eeworm.com/read/210234/15203217

udo jsq1_tw.udo

-- ProjNav VHDL simulation template: jsq1_tw.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/210234/15203235

hb_cmds

-proj e:\vhdl\past\pingche -t f5_tw.tbw -source f5q_2.vhdl -entity f5 -ipcport 49588
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www.eeworm.com/read/210234/15203251

log coregen.log

# Xilinx CORE Generator 6.2i # User = zsx Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\VHDL\past\pingche\coregen.log # busformat=BusFormatAngleB
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www.eeworm.com/read/210233/15203453

lfp yj.lfp

# begin LFP file E:\VHDL\waitpast\qiangdaqi4ren\yj.lfp designfile qdkz.ngd IO_GROUP "wx" ; IO_GROUP "q" ; NET "wx" IO_GROUP="wx" ; NET "wx" IO_GROUP="wx" ; NET "wx" IO_GROUP="wx" ;
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www.eeworm.com/read/210233/15203493

gfl qiangdaqi4ren.gfl

# VHDL : Create Schematic Symbol __projnav/tb.rsp sel.spl __projnav/vhd2spl.err # VHDL : Create Schematic Symbol __projnav/tb.rsp lock.spl __projnav/vhd2spl.err # VHDL : Create Schematic Symbo
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www.eeworm.com/read/210233/15203512

hb_cmds

-proj e:\vhdl\waitpast\qiangdaqi4ren -t lock_tw.tbw -source lock.vhdl -entity lock -ipcport 49350
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www.eeworm.com/read/210232/15203668

log coregen.log

# Xilinx CORE Generator 6.3i # User = student32 Initializing default project... Loading plug-ins... All runtime messages will be recorded in E:\zsx\dianzheng\coregen.log # busformat=BusFormatAngl
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www.eeworm.com/read/210231/15203743

udo m59.udo

-- ProjNav VHDL simulation template: m59.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation commands
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www.eeworm.com/read/210231/15203780

prj digclk.prj

vhdl work "s59.vhdl" vhdl work "bskz.vhdl" vhdl work "MIN.vhdl" vhdl work "LCD1602.vhd" vhdl work "HOUR.vhdl" vhdl work "FPQ1S.vhdl" vhdl work "FEN_SOUND.vhdl" vhdl work "digclk.vhf"
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