coregen.log

来自「简易数字频率计」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.2i
# User = zsx
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\VHDL\past\pingche\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\VHDL\past\pingche
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\VHDL\past\pingche
SETPROJECT .
Set current Project to E:\VHDL\past\pingche
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1257
XIPCPJSENDCORES spartan2